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Deep Insight into Channel Engineering of Sub-3 nm -Node P-Type Nanosheet Transistors with a Quantum Transport Model

By Afshan Khaliq, Shuo Zhang, Jun Z. Huang, Kai Kang, and Wen-Yan Yin
Progress In Electromagnetics Research, Vol. 174, 75-88, 2022


Based on a self-consistent Schrodinger-Poisson solver and top-of-the-barrier model, a quantum transport simulator of p-type gate-all-around nanosheet FET is developed. The effects of material (Si/Ge), stress, crystallographic orientation, and cross-sectional size are deeply explored by numerical simulations for the device performance at the sub-3 nm technology node. A strain-dependent 6-band k.p Hamiltonian is incorporated into the model for a more accurate calculation of E-k dispersion in the strain-perturbed valence band structure, where the curvature, energy shift, and splitting of subbands are investigated in detail for hole transport properties. Further, the effect of channel engineering is comprehensively analyzed, by evaluating density-of-states effective mass, average injection velocity, mobility, current density distributions, and the current-voltage characteristics. An effective performance improvement from 2GPa compressive stress is obtained in [100]/(001) and [110]/(001) channels, with a 7% enhancement of ON-current in Ge nanosheet FETs. While a wider channel cross-section improves the drive current by increasing the effective channel width, a smaller cross-sectional width yields an average increase up to 29% in the ON-state injection velocity due to stronger quantum confinement.


Afshan Khaliq, Shuo Zhang, Jun Z. Huang, Kai Kang, and Wen-Yan Yin, "Deep Insight into Channel Engineering of Sub-3 nm -Node P-Type Nanosheet Transistors with a Quantum Transport Model," Progress In Electromagnetics Research, Vol. 174, 75-88, 2022.


    1. Loubet, N., T. Hook, P. Montanini, C.-W. Yeung, S. Kanakasabapathy, and M. Guillorn, "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," Proceedings Symposium VLSI Technology, Vol. 5, No. 1, 14-15, 2017, doi: 10.23919/VLSIT.2017.7998183.

    2. Jang, D., et al., "Device exploration of nanosheet transistors for sub-7-nm technology node," IEEE Transactions on Electron Devices, Vol. 64, No. 4, 2707-2713, 2017, doi: 10.1109/TED.2017.2695455.

    3. Nagy, D., G. Indalecio, A. J. Garcia-Loureiro, M. A. Elmessary, K. Kalna, and N. Seoane, "FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability," IEEE Journal of Electron Devices Society, Vol. 6, No. 1, 332-340, 2018, doi: 10.1109/JEDS.2018.2804383.

    4. Zhang, S., et al., "Design considerations for Si- and Ge-stacked nanosheet pMOSFETs based on quantum transport simulations," IEEE Transactions on Electron Devices, Vol. 67, No. 1, 26-32, 2020, doi: 10.1109/TED.2019.2954308.

    5. Sun, Y., S. E. Thompson, and T. Nishida, "Physics of strain effects in semiconductors and metal- oxide-semiconductor field-effect transistors," Journal of Applied Physics, Vol. 101, No. 10, 2007, doi: 10.1063/1.2730561.

    6. Yao, J., et al., "Physical insights on quantum confinement and carrier mobility in Si, Si0.45Ge0.55, Ge gate-all-around NSFET for 5 nm technology node," IEEE Journal of Electron Devices Society, Vol. 6, 841-848, 2018, doi: 10.1109/JEDS.2018.2858225.

    7. Teherani, J. T., "A comprehensive theoretical analysis of hole ballistic velocity in Si, SiGe, and Ge: Effect of uniaxial strain, crystallographic orientation, body thickness, and gate architecture," IEEE Transactions on Electron Devices, Vol. 64, No. 8, 3316-3323, 2017, doi: 10.1109/TED.2017.2708691.

    8. Mohapatra, E., T. P. Dash, J. Jena, S. Das, and C. K. Maiti, "Strain induced variability study in gate-all-around vertically-stacked horizontal nanosheet transistors," Physica Scripta, Vol. 95, No. 6, 2020, doi: 10.1088/1402-4896/ab89f5.

    9. Khakifirooz, A. and D. A. Antoniadis, "Transistor performance scaling: The role of virtual source velocity and its mobility dependence," IEEE International Electron Devices Meeting, 1-4, 2006, doi: 10.1109/IEDM.2006.346873.

    10. Dash, T. P., S. Dey, S. Das, E. Mohapatra, J. Jena, and C. K. Maiti, "Strain-engineering in nanowire field-effect transistors at 3 nm technology node," Physica E Low-Dimensional System and Nanostructures, Vol. 118, 113964, 2020, doi: 10.1016/j.physe.2020.113964.

    11. Maegawa, T., T. Yamauchi, T. Hara, H. Tsuchiya, and M. Ogawa, "Strain effects on electronic bandstructures in nanoscaled silicon: From bulk to nanowire," IEEE Transactions on Electron Devices, Vol. 56, No. 4, 553-559, 2009, doi: 10.1109/TED.2009.2014185.

    12. Zhang, J.-H., Q.-A. Huang, H. Yu, and S.-Y. Lei, "Orientation effects in ballistic high-strained p-type Si nanowire FETs," Sensors, Vol. 9, No. 4, 2746-2759, 2009, doi: 10.3390/s90402746.

    13. Thompson, S. E., G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs," IEEE International Electron Devices Meeting, 221-224, 2005, doi: 101109/IEDM.2004.1419114.

    14. Sun, Y., X. Yu, R. Zhang, B. Chen, and R. Cheng, "The past and future of multi-gate field-effect transistors: Process challenges and reliability issues," Journal of Semiconductor, Vol. 42, No. 2, 2021, doi: 10.1088/1674-4926/42/2/0231102.

    15. Stanojevic, Z., V. Sverdlov, O. Baumgartner, and H. Kosina, "Subband engineering in n-type silicon nanowires using strain and confinement," Solid State Electronics, Vol. 70, 73-80, 2012, doi: 10.1016/j.sse.2011.11.022.

    16. Zhang, L., J. He, J. Zhang, F. Liu, Y. Fu, Y. Song, and X. Zhang, "An analytic model for Ge/Si core/shell nanowire MOSFETs considering drift-diffusion and ballistic transport," 10th Int'l Symposium on Quality Electronic Design, 2009, doi: 10.1109/ISQED.2009.4810359.

    17. Xu, X. and J. Mahanty, "The influence of Si delta doping on the electronic structure of AlGaAs- GaAs-AlGaAs single quantum wells," Journal of Physics: Condense Matter, Vol. 6, No. 25, 4745-4762, 1994.

    18. Moussavou, M., N. Cavassilas, E. Dib, and M. Bescond, "Influence of uniaxial strain in Si and Ge p-type double-gate metal-oxide-semiconductor field effect transistors," Journal of Applied Physics, Vol. 118, No. 11, 2015, doi: 10.1063/1.4930567.

    19. Huang, J. Z., L. Zhang, P. Long, M. Povolotskyi, and G. Klimeck, "Quantum transport simulation of III-V TFETs with reduced-order kp method," Tunneling Field Effect Transistor Technology, 151-180, 2016, doi: 10.1007/978-3-319-31653-6_6.

    20. Ma, Z.-H., W. C. Chew, and L. J. Jiang, "A novel fast solver for Poisson's equation with Neumann boundary condition," Progress In Electromagnetic Research, Vol. 136, 195-209, 2013.

    21. Neophytou, N., A. Paul, and G. Klimeck, "Bandstructure effects in silicon nanowire hole transport," IEEE Transactions Nanotechnology, Vol. 55, No. 6, 1286-1297, 2008, doi: 10.1109/TNANO.2008.2006272.

    22., "IEEE International Roadmap for Devices and Systems --- IEEE IRDS,", 2020.

    23. Wang, J., A. Rahman, G. Klimeck, and M. Lundstrom, "Bandstructure and orientation effects in ballistic Si and Ge nanowire FETs," IEEE International Electron Devices Meeting, Vol. 2005, 530-533, 2005, doi:10.1109/IEDM.2005.1609399.

    24. Anantram, M. P., M. S. Lundstrom, and D. E. Nikonov, "Modeling of nanoscale devices," Proceedings of the IEEE, Vol. 96, No. 9, 1509-1510, 2008, doi: 10.1109/JPROC.2008.927311.

    25. Datta, S., Quantum Transport: Atom to Transistor, Cambridge University Press, 2005.

    26. Lundstrom, M. S. and D. A. Antoniadis, "Compact models and the physics of nanoscale FETs," IEEE Transactions on Electron Devices, Vol. 61, No. 2, 225-233, 2014, doi: 10.1109/TED.2013.2283253.

    27. Wang, R., Y. Zhang, G. H. Chen, and C. Y. Yam, "Quantum mechanical modeling of electron- photon interactions in nanoscale devices," Progress In Electromagnetic Research, Vol. 154, 163-170, 2015.