In this research project, the hardware implementation of a Field-Programmable Gate Array (FPGA) based Fast Fourier Transform (FFT) will be carried out by using Verilog Hardware Description Language (HDL). Since FFT serves as the core for the Range Doppler Algorithm (RDA) in Synthetic Aperture Radar (SAR) processing, it is of paramount importance to evaluate the algorithm and its computational complexity for the design of an efficient FFT hardware architecture. The design process and Verilog hardware description language which is used to describe and model a digital FPGA-based SAR processor will be introduced. Detailed explanation of the hardware implementation for FFT and Inverse Fast Fourier Transform (IFFT) in SAR processing are thus presented. The performance evaluations of the proposed processors including the comparison of the proposed processor with MATLAB-based processor, timing considerations of the processor, and lastly the hardware resources usage considerations are delivered at the end of this paper.
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