3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging efficiency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Specifically, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior. In this letter, 5x50 μm TSVs are manufactured using a via-mid integration scheme and characterized using S-Parameters up to 65 GHz. At 50 GHz, the measured attenuation constant is 0.35 dB/via with a time delay of 0.7 ps/via.
2. Arden, W., M. Brillouet, P. Cogez, M. Graef, B. Huizing, and R. Mahnkopf, "More-than-Moore,", White Paper, Version 2, 14, 2010.
3. I-Micronews, "Samsung presents new 3D TSV Packaging Roadmap," Advanced Packaging, Retrieved Feb. 23, 2014, from http://www.i-micronews.com/news/Samsung-3D-TSV-Packaging-Roadmap,4047.html.
4. Batra, P., et al., "Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology," 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Uni¯ed Conference (S3S), Vol. 43, No. 1-2, 2013, Doi: 10.1109/S3S.2013.6716515.
5. Beyne, E., "3D system integration technologies," 2006 International Symposium on VLSI Technology, Systems, and Applications, 1-9, Apr. 2006.
doi:10.1109/VTSA.2006.251113
6. Dong, X. and Y. Xie, "System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)," Asia and South Pacific Design Automation Conference, ASP-DAC 2009, 234-241, Jan. 2009.
doi:10.1109/ASPDAC.2009.4796486
7. Knickerbocker, J. U., et al., "3D silicon integration," 58th Electronic Components and Technology Conference, ECTC 2008, 538-543, May 2008.
doi:10.1109/ECTC.2008.4550025
8. Johnson, H. W. and M. Graham, High-speed Signal Propagation: Advanced Black Magic, Prentice Hall/PTR, Upper Saddle River, NJ, 2003.
9. Yu, C. L., et al., "TSV process optimization for reduced device impact on 28nm CMOS," 2011 Symposium on VLSI Technology (VLSIT), 138-139, Jun. 14-16, 2011.
10. Kawano, M., et al., "A 3D packaging technology for 4 Gbit stacked DRAM with 3 Gbps data transfer," International Electron Devices Meeting, IEDM' 06, 1-4, Dec. 11-13, 2006.
11. Arkalgud, S., "Via mid through silicon vias --- The manufacturability outlook," 2010 International Symposium on VLSI Design Automation and Test (VLSI-DAT), 17-18, Apr. 26-29, 2010.
12. Chang, Y.-C., S. S. H. Hsu, D. Chang, J. Lee, S. Lin, and Y.-Z. Juang, "A de-embedding method for extracting S-parameters of vertical interconnect in advanced packaging," 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 219-222, 2011, Doi: 10.1109/EPEPS.2011.6100231.
doi:10.1109/EPEPS.2011.6100231
13. Yau, K. H., et al., "On-wafer S-parameter de-embedding of silicon active and passive devices up to 170 GHz," 2010 IEEE MTT-S International Microwave Symposium Digest (MTT), 600-603, May 2010.
doi:10.1109/MWSYM.2010.5518218
14. Cressler, J. D., "Measurement and modeling," Silicon Heterostructure Handbook, Material, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-layer Epitaxy, 781-792, CRC Press, Boca Raton, Florida, 2006.
15., "Manual of ANSYS HFSS v.13," ANSYS Inc., Canonsburg, PA, 2011.
16. Xu, Z. and J. Lu, "Through-silicon-via fabrication technologies, passives extraction, and electrical modeling for 3-D integration/packaging," IEEE Transactions on Semiconductor Manufacturing, Vol. 26, No. 1, 23-34, 2013, Doi: 10.1109/TSM.2012.2236369.
doi:10.1109/TSM.2012.2236369
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